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Texas Instruments /MSP432P4111 /WDT_A /WDTCTL

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Interpret as WDTCTL

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15 1211 87 43 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (WDTIS_0)WDTIS0 (WDTCNTCL_0)WDTCNTCL 0 (WDTTMSEL_0)WDTTMSEL 0 (WDTSSEL_0)WDTSSEL 0 (WDTHOLD_0)WDTHOLD 0WDTPW

WDTSSEL=WDTSSEL_0, WDTCNTCL=WDTCNTCL_0, WDTIS=WDTIS_0, WDTHOLD=WDTHOLD_0, WDTTMSEL=WDTTMSEL_0

Description

Watchdog Timer Control Register

Fields

WDTIS

Watchdog timer interval select

0 (WDTIS_0): Watchdog clock source / (2^(31)) (18:12:16 at 32.768 kHz)

1 (WDTIS_1): Watchdog clock source /(2^(27)) (01:08:16 at 32.768 kHz)

2 (WDTIS_2): Watchdog clock source /(2^(23)) (00:04:16 at 32.768 kHz)

3 (WDTIS_3): Watchdog clock source /(2^(19)) (00:00:16 at 32.768 kHz)

4 (WDTIS_4): Watchdog clock source /(2^(15)) (1 s at 32.768 kHz)

5 (WDTIS_5): Watchdog clock source / (2^(13)) (250 ms at 32.768 kHz)

6 (WDTIS_6): Watchdog clock source / (2^(9)) (15.625 ms at 32.768 kHz)

7 (WDTIS_7): Watchdog clock source / (2^(6)) (1.95 ms at 32.768 kHz)
WDTCNTCL

Watchdog timer counter clear

0 (WDTCNTCL_0): No action

1 (WDTCNTCL_1): WDTCNT = 0000h
WDTTMSEL

Watchdog timer mode select

0 (WDTTMSEL_0): Watchdog mode

1 (WDTTMSEL_1): Interval timer mode
WDTSSEL

Watchdog timer clock source select

0 (WDTSSEL_0): SMCLK

1 (WDTSSEL_1): ACLK

2 (WDTSSEL_2): VLOCLK

3 (WDTSSEL_3): BCLK
WDTHOLD

Watchdog timer hold

0 (WDTHOLD_0): Watchdog timer is not stopped

1 (WDTHOLD_1): Watchdog timer is stopped
WDTPW

Watchdog timer password

Links

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Register License

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data